The RAD Flow

Introduction

The RAD flow is an open source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration devices (RADs). These devices incorporate conventional FPGA fabrics, several coarse-grained domain-specialized accelerator blocks, and high-performance packet-switched networks-on-chip (NoCs) for system-level communication. The flow consists of the following tools:

• RAD-Sim: A SystemC simulator for rapid design space exploration and architecture-application co-design

• RAD-Gen: A push button tool for silicon area/timing/power implementation results of hard (ASIC) RAD components, FPGA fabric circuitry, and different 3D considerations (Under development)

How to Cite

The following paper may be used as a general citation for RAD-Sim:

@article{rad-sim,
   title={{Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices}},
   author={Boutros, Andrew and Nurvitadhi, Eriko and Betz, Vaughn},
   journal={IEEE Access},
   volume={10},
   pages={95067--95082},
   year={2022},
   publisher={IEEE}
}

RAD-Sim Documentation

• Quick Start Guide
  • Installing C++ Compiler and CMake
  • Installing SystemC
  • Installing Python Dependencies
  • Building RAD-Sim
  • Running RAD-Sim
• Create Your First RAD-Sim Module
  • Overview
  • Sender Module
  • Reciever Module
  • Producer_Consumer Top
  • Producer_Consumer System
  • Configurations
  • Running the Design
• Code Structure
  • Overview
  • Simulator Infrastructure (sim)
  • Application Designs (example-designs)
    • Modules Directory (modules/)
    • Design Top-level (<design_name>_top.{cpp/hpp})
    • Design Testbench (<design_name>_driver.{cpp/hpp})
    • Design System (<design_name>_system.{cpp/hpp})
    • Clock Settings File (<design_name>.clks)
    • NoC Placement File (<design_name>.place)
    • CMakeLists File (CMakeLists.txt)
    • RAD-Sim Configuration File (config.yml)
• Compiling a RAD-Sim Module with RTL
  • Installation
  • Setting Up a Project with RTL
  • RTL CMakeLists
  • Wrapper Files
  • Automatic Wrapper Files Generation
    • AXI-S/AXI-MM Formatting Requirement
    • Port Map File Format
• Examples
  • Example: Adder Design
    • Design Architecture
    • File Structure Overview
    • Prerequisites
    • Components
    • Running the Example
  • Example: MLP RTL Co-Simulation Design
    • Design Architecture
    • Prerequisites
    • Components
    • AXI-S Data Format
    • Instruction Format
    • Running the Example
• RAD-Sim Developers
  • RAD-Sim Testing Infrastructure
    • Python Scripts Tests
    • MLP Test
    • MLP Co-Simulation Test
    • DLRM Test
    • NPU Tests

RAD-Gen Documentation

• Quick Start Guide